Advanced semiconductor manufacturing today involves the movements of wafers from start to finish through hundreds of steps. Each step can have multiple choices of tools, chambers, recipes, etc. The processing route(s) for the wafers are determined mainly based on tool availability, i.e., capacity utilization, in order to move wafers as fast as possible through the route and typically occurs without consideration of yield and other factors. However, the routes for processing the wafers or wafer lots are typically not determined by taking into account, to a significant extent, known processing tool signature as well as characteristics of the wafers such as the purpose of the wafers, inline test and measurement results, and defect inspection results, in particular, tool yield signature and wafer yield signature.
FIG. 1 shows an example of different types of processing tools 10-13, 20-23, 30-33 and 40-43 using the same four process steps. In this example, two processing routes R1 and R2 are shown.
In processing route R1, the wafers leaving tool 11 are transferred to tool 21 because tool 21 is either waiting for wafers or has fewer wafers waiting for processing than tools 20, 22 and 23, i.e., the processing route is based on capacity utilization considerations. The wafers leaving tool 21 are transferred to tool 31, and are then transferred from tool 31 to tool 41, for similar reasons, i.e., because tools 31 and 41 are either waiting for wafers or has fewer wafers waiting for processing than, respectively, tools 30, 32 and 33 and tools 40, 42 and 43.
In processing route R2, the wafers leaving tool 12 are similarly transferred to tool 22 because tool 22 is either waiting for wafers or has fewer wafers waiting for processing than tools 20, 21 and 23. The wafers leaving tool 22 are similarly transferred to tool 33 because tool 33 is either waiting for wafers or has fewer wafers waiting for processing than tools 30, 31 and 32, and are then transferred to tool 43 because tool 43 is similarly either waiting for wafers or has fewer wafers waiting for processing than tools 40, 41 and 42.
The above-noted routes are typically not determined by the known process variations of the processing tools. It is known, for example, that some tools generate consistent problems affecting one aspect of the wafers while other tools generate consistent problems affecting other aspects of the wafers. Thus, for example, some etching tools may consistently over etch an edge region of the wafers, while other etching tools under etch a center region of the wafers, or vice versa. Also, some deposition tools may consistently over deposit material in one zone region of the wafers, while other deposition tools under deposit material in another zone region of the wafers, or vice versa. Furthermore, all processing tools drift with time, e.g., their ability to produce wafers with consistent characteristics and dimensions changes. The tools, however, can be re-centered, i.e., brought back to the point that they produce less variability from wafer to wafer or wafer lot to wafer lot. The need for such re-centering is typically determined by numerous considerations such as, e.g., the tool's maintenance schedule and feedback or measurements provided from monitors, processing results, inspection reports, etc.
The problem, however, is that there is usually a time delay between feedback and tool adjustment. For example, most tools are qualified on a 24 hour or longer interval. A shorter qualification interval is however expensive because it typically requires using more monitors and typically requires the non-productive idling of the tool for qualification and awaiting results thereof.
Awaiting feedback from the wafers is even less effective because the data from the wafers is typically not be available in a timely enough manner. Furthermore, performing excessive readjustment of the tool (even when the tool is in the normal statistical controlled specification limit) can also cause too much interruption of the tool, and may even cause chamber instability.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described herein.